1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device capable of preventing process failure caused by a step difference between a cell region and a peripheral region and preventing yield loss derived from such process failure.
2. Description of the Prior Art
As semiconductor devices have come highly integrated, there is difficulty in making a contact between upper and lower patterns, that is, it is difficult to form a contact between a junction area and a bit line and between a junction area and a capacitor.
To solve the above problems, a landing plug poly is currently adopted in most of semiconductor manufacturing processes in order to form a stable electric contact between upper and lower patterns. Electric connection between the junction area and the bit line and between the junction area and the capacitor is stably achieved trough such a landing plug poly.
According to a conventional semiconductor manufacturing process, after a gate has been formed, a BPSG layer is deposited on the gate as an insulating interlayer. Then, an annealing process is carried out with respect to the BPSG layer such that the BPSG layer is melted and flows into a gap, thereby completely filling the gap.
However, such a conventional semiconductor manufacturing process may necessarily cause a step difference between a cell region and a peripheral region, so it is necessary to recess the cell region by performing a cell-open mask forming process and an etching process by using a cell-open mask in order to ensure reliability of the following processes. Therefore, the conventional semiconductor manufacturing process not only causes some trouble in the manufacture of semiconductor devices, but also increases manufacturing costs.
In addition, in order to form the landing plug poly, the conventional semiconductor manufacturing process carries out a CMP (chemical mechanical polishing) process by using alkalic slurry after depositing a polysilicon layer. If the CMP process is carried out by using such alkalic slurry, a dishing phenomenon may occur in surfaces of a BPSG layer including insulating interlayer material, and the polysilicon layer including plug material.
For this reason, an oxide layer must be additionally deposited in order to solve the above dishing problem, thereby causing some trouble in the manufacture of semiconductor devices.
In particular, polishing residual may exist in a dishing region without being completely removed through a following cleaning process. In this case, a bridge is created between bit line contacts or storage node contacts, thereby causing yield loss.